As MOS technologies become smaller, the power supply voltages must be lowered. However, analog circuits designed from the smaller technologies must process signals of the same amplitude, requiring a similar dynamic range in spite of the lower supply voltages. In order to provide this dynamic range, circuit designs often employ fully differential operational amplifiers.
A fully differential operational amplifier has two inputs (V.sub.in.sup.+ and V.sub.in.sup.-) and two output voltages (V.sub.out.sup.+ and V.sub.out.sup.-). The output voltages ideally are symmetrical about a common-mode output voltage (V.sub.cmo). However, no information about the common-mode output voltage is fed back to the inputs in a typical fully differential amplifier. The common-mode output voltage is very sensitive to voltage perturbations and environmental changes.
One approach to the common-mode bias problem is the use of a switched-capacitor circuit. While this circuit sufficient in some applications, it requires a reset period for every clock cycle. Hence, it is inappropriate for applications such as continuous time filters where a reset period is not always available.
Another solution has been to design the output stage of the operational amplifier with parallel MOS devices operating in the ohmic region in a feedback loop designed to adjust the output voltages in accordance with a common-mode bias imbalance. However, this design sufficiently limits the output voltage swing of the output stage and exhibits limited loop gain. This presents a problem as the power supply voltages become smaller with improved technology. As a result, the precision with which the common-mode output bias point can be set is poor.
Therefore, a need has arisen in the industry for a fully differential operational amplifier design allowing precise setting of the common-mode output bias point without limiting the output voltage swing of the amplifier.